1ヶ月ほどかかってようやく仕様が決まりました。いや〜長かった。202コも命令があるのでなかなか大変でしたよ。
もっとも、まだ実際に回路をつくってテストしたわけではないのでこれから変更される可能性もあるのですがね。
なお、仕様決定にあたり以下の本やページを参考にしました。とても参考になりました。ありがとうございます。
https://ndlsearch.ndl.go.jp/books/R100000002-I000001418670
http://www.zilog.com/docs/z80/um0080.pdf
https://www.zilog.com/docs/z80/ps0178.pdf
http://www.z80.info/zip/z80-interrupts.pdf
http://www.kazumi-kikou.com/pdf/TMPZ84C00AP.pdf
http://www.maroon.dti.ne.jp/youkan/mz700/z80cycle.html
http://mydocuments.g2.xrea.com/html/p6/z80ref.html
- インターフェース
- レジスタ
- フリップフロップ
- パスフラグ
- ALU
- デコーダ
- 標準サイクル
- 割り込みサイクル
- 命令
- 8bitデータ移動
- 16bitデータ移動
- 交換・ブロック転送および検索
- 8bit算術・論理演算
- ADD A,r
- ADD A,n
- ADD A,(HL)
- ADD A,(IX+d)
- ADD A,(IY+d)
- ADC A,r
- ADC A,n
- ADC A,(HL)
- ADC A,(IX+d)
- ADC A,(IY+d)
- SUB r
- SUB n
- SUB (HL)
- SUB (IX+d)
- SUB (IY+d)
- SBC r
- SBC n
- SBC (HL)
- SBC (IX+d)
- SBC (IY+d)
- AND r
- AND n
- AND (HL)
- AND (IX+d)
- AND (IY+d)
- OR r
- OR n
- OR (HL)
- OR (IX+d)
- OR (IY+d)
- XOR r
- XOR n
- XOR (HL)
- XOR (IX+d)
- XOR (IY+d)
- CP r
- CP n
- CP (HL)
- CP (IX+d)
- CP (IY+d)
- INC r
- INC (HL)
- INC (IX+d)
- INC (IY+d)
- DEC r
- DEC (HL)
- DEC (IX+d)
- DEC (IY+d)
- 汎用算術演算およびCPU制御
- 16bit算術演算
- 循環および桁移動
- bit操作および判定
- 飛び越し命令
- サブルーチン接続および戻り命令
- 入力および出力命令
- 命令分布
インターフェース
種類 | io | とりうる値 | デフォルト値 | 名前 |
---|---|---|---|---|
アドレスバス | out | 1/0/Z | Z | A0~A15 |
データバス | in/out | 1/0/Z | Z | D0~D7 |
バス制御 | in | /BUSRQ | ||
out | 1/0 | 1 | /BUSAK | |
主記憶制御 | out | 1/0/Z | 1 | /MREQ |
out | 1/0/Z | 1 | /RD | |
out | 1/0/Z | 1 | /WR | |
out | 1/0 | 1 | /RFSH | |
入出力制御 | out | 1/0/Z | 1 | /IORQ |
その他の制御 | out | 1/0 | 1 | /M1 |
in | /RESET | |||
in | /WAIT | |||
out | 1/0 | 1 | /HALT | |
割り込み入力 | in | /NMI | ||
in | /INT | |||
クロック | in | /CLK | ||
電源 | in | VCC(5V) | ||
in | GND |
レジスタ
公式レジスタ
アキュムレータ (A)
8bit
EX系命令で交換できる
フラグレジスタ (F)
8bit
EX系命令で交換できる
フラグ書き込みが可能
第7bit | 第6bit | 第5bit | 第4bit | 第3bit | 第2bit | 第1bit | 第0bit |
---|---|---|---|---|---|---|---|
S | Z | (X) | H | (Y) | P/V | N | C |
S: ALUの結果が負
Z: ALUの結果が0
H: ALUにおいてハーフキャリー/ハーフボローが発生
P: ALUの結果が偶パリティ
V: ALUにおいてオーバーフローが発生
N: ALUで減算を実行
C: ALUにおいてキャリー/ボローが発生
キャリー・ボロー・ハーフキャリー・ハーフボロー・パリティ・オーバーフローについてはALUの項で解説します。
汎用レジスタ (B,C,D,E,H,L)
8bit
EX系命令で交換できる
裏レジスタ (A',F',B',C',D',E',H',L')
8bit
EX系命令で交換できる
プログラムカウンタ (PC)
16bit
インクリメント可能
スタックポインタ (SP)
16bit
インクリメント・デクリメント可能
インデックスレジスタ (IX,IY)
16bit
割り込み番地指定レジスタ (I)
8bit
リフレッシュレジスタ (R)
8bit
インクリメントが可能(ただし、第7bitは不変)
非公式レジスタ
命令1バイト経過Tサイクル (XPT)
5bit
クロックに合わせて自動でインクリメントしていく
Write不可
HaltとResetが可能
データレジスタ (Dt,Dtex)
8bit
位相半ずらしデータレジスタ (Dtcs)
8bit
クロックがhighのときに、Dinから読み込みできる
Write不可
命令レジスタ (OP,OPold)
8bit
WriteはOPのみ可能(lowが入る)
OPからOPoldへのスライドが可能
フリップフロップ
公式フリップフロップ
IFF1/2
割り込み許可用
IMFa/b
IM 0/1/2 で指定する割り込みモード用
IMFa | IMFb | モード |
---|---|---|
0 | 0 | 0 |
0 | 1 | NOT USED |
1 | 0 | 1 |
1 | 1 | 2 |
非公式フリップフロップ
検出系(T)
TINT:2 負論理 ↓入力と↑入力がある ↓入力は出力を半クロックずらす 使用時はAND
TNMI:2 負論理 ↓入力と↑入力がある ↓入力は出力を半クロックずらす 使用時はAND
TWAIT:1 負論理 ↑入力 寿命1サイクル
TRSET:3 負論理 3サイクルカウント用 使用は3つ目
保持系(L)
LHALT: if(LHALT=1)→PI_Flag_HALT
サイクル系(C)
XPTと組み合わせてパスフラグを出力する
CM1
CMR
CMA
CBUSRQ
CRESET
CNMI
CINT0
CINT0_RST
CINT0_CALL
CINT1
CINT2
M1型命令系(X)
XIX(11 011 101): 1
XIX4_0/1(XIX→11 001 011): 2
XIY(11 111 101): 1
XIY4_0/1(XIY→11 001 011): 2
XOTR(11 101 101): 1
XBIT(11 001 011): 1
MR型命令系(I)
XPTと組み合わせてパスフラグを出力する
全168のパスフラグを構成するため、8つのフリップフロップを使用
ILDrn_A/B/C/D/E/H/L: 7
ILDr(IX+d)_A/B/C/D/E/H/L: 7
ILDr(IY+d)_A/B/C/D/E/H/L: 7
ILD(IX+d)r_A/B/C/D/E/H/L: 7
ILD(IY+d)r_A/B/C/D/E/H/L: 7
ILD(HL)n: 1
ILD(IX+d)n_0/1: 2
ILD(IY+d)n_0/1: 2
ILDA(nn)_0/1: 2
ILD(nn)A_0/1: 2
ILDddnn_BC/DE/HL/SP_0/1: 8
ILDIXnn_0/1: 2
ILDIYnn_0/1: 2
ILDHL(nn)_0/1: 2
ILDdd(nn)_BC/DE/HL/SP_0/1: 8
ILDIX(nn)_0/1: 2
ILDIY(nn)_0/1: 2
ILD(nn)HL_0/1: 2
ILD(nn)dd_BC/DE/HL/SP_0/1: 8
ILD(nn)IX_0/1: 2
ILD(nn)IY_0/1: 2
IADDAn: 1
IADDA(IX+d): 1
IADDA(IY+d): 1
IADCAn: 1
IADCA(IX+d): 1
IADCA(IY+d): 1
ISUBAn: 1
ISUBA(IX+d): 1
ISUBA(IY+d): 1
ISBCAn: 1
ISBCA(IX+d): 1
ISBCA(IY+d): 1
IANDn: 1
IAND(IX+d): 1
IAND(IY+d): 1
IORn: 1
IOR(IX+d): 1
IOR(IY+d): 1
IXORn: 1
IXOR(IX+d): 1
IXOR(IY+d): 1
ICPn: 1
ICP(IX+d): 1
ICP(IY+d): 1
IINC(IX+d): 1
IINC(IY+d): 1
IDEC(IX+d): 1
IDEC(IY+d): 1
IRLC(IX+d)_0/1: 2
IRLC(IY+d)_0/1: 2
IRL(IX+d)_0/1: 2
IRL(IY+d)_0/1: 2
IRRC(IX+d)_0/1: 2
IRRC(IY+d)_0/1: 2
IRR(IX+d)_0/1: 2
IRR(IY+d)_0/1: 2
ISLA(IX+d)_0/1: 2
ISLA(IY+d)_0/1: 2
ISRA(IX+d)_0/1: 2
ISRA(IY+d)_0/1: 2
ISRL(IX+d)_0/1: 2
ISRL(IY+d)_0/1: 2
IJPnn_0/1: 2
IJPccnn_0/1/2/3/4/5/6/7_0/1: 16
IJRe: 1
IJRCe: 1
IJRNCe: 1
IJRZe: 1
IJRNZe: 1
IDJNZe: 1
ICALLnn_0/1: 2
IINA(n): 1
IOUT(n)A: 1
パスフラグ (P)
動作を決定する正負状態を表すものを言いたかったのですが、 フラグ という言葉を使えなかったのでパスフラグとでも呼称しておきます。
レジスタ (PR)
書き込み
Write_A: high
Write_F: low
Write_B: high
Write_C: low
Write_D: high
Write_E: low
Write_H: high
Write_L: low
Write_PC_high
Write_PC_low
Write_SP_high
Write_SP_low
Write_IX_high
Write_IX_low
Write_IY_high
Write_IY_low
Write_Dt: low
Write_Dtex: high
Write_R: low
Write_I: high
Write_OP: low InvertInの影響を受けない
その他
Ex_AF_A’F’: AF↔︎A'F'
Ex_DE_HL: DE↔︎HL
Exx: BCDEHL↔︎B'C'D'E'H'L'
Inc_PC
Inc_SP
Inc_R: R_7は不変
Dec_SP
Reset_XPT
Halt_XPT
SlideOP(OP→OPold)
フラグ (PF)
書き込み
いずれかが1の時、X<-ALU_3,Y<-ALU_5
Write_S
Write_Z
Write_H
Write_P/V
Write_N
Write_C
入力選択
Select_S_bitZ
Select_Z_bitZ
Select_H_bitZ
Select_P/V_bitZ
Select_N_bitZ
Select_C_bitZ
フリップフロップ (P2)
割り込み公式
Set_IFF1
Set_IFF2
Reset_IFF1
Reset_IFF2
EvacuateIFF: IFF2←IFF1
RestoreIFF: IFF1←IFF2
IM0
IM1
IM2
検出系(T)
Reset_TNMI: TNMI←1
Reset_TINT: TINT←1
Reset_TRESET TRESET_0/1/2←1
保持系(L)
Set_LHALT
Reset_LHALT
サイクル系(C)
Set_CM1
Set_CMR
Set_CMA
Set_CBUSRQ
Set_CRESET
Set_CNMI
Set_CINT0
Set_CINT0_RST
Set_CINT0_CALL
Set_CINT1
Set_CINT2
Reset_CM1
Reset_CMR
Reset_CMA
Reset_CBUSRQ
Reset_CRESET
Reset_CNMI
Reset_CINT
M1型命令系(X)
Set_XIX
Set_XIX4_0/1
Set_XIY
Set_XIY4_0/1
Set_XOTR
Set_XBIT
Reset_XIX
Reset_XIX4
Reset_XIY
Reset_XIY4
Reset_XOTR
Reset_XBIT
MR型命令系(I)
Set_ILDrn_A/B/C/D/E/H/L
Set_ILDr(IX+d)_A/B/C/D/E/H/L
Set_ILDr(IY+d)_A/B/C/D/E/H/L
Set_ILD(IX+d)r_A/B/C/D/E/H/L
Set_ILD(IY+d)r_A/B/C/D/E/H/L
Set_ILD(HL)n
Set_ILD(IX+d)n_0/1
Set_ILD(IY+d)n_0/1
Set_ILDA(nn)_0/1
Set_ILD(nn)A_0/1
Set_ILDddnn_BC/DE/HL/SP_0/1
Set_ILDIXnn_0/1
Set_ILDIYnn_0/1
Set_ILDHL(nn)_0/1
Set_ILDdd(nn)_BC/DE/HL/SP_0/1
Set_ILDIX(nn)_0/1
Set_ILDIY(nn)_0/1
Set_ILD(nn)HL_0/1
Set_ILD(nn)dd_BC/DE/HL/SP_0/1
Set_ILD(nn)IX_0/1
Set_ILD(nn)IY_0/1
Set_IADDAn
Set_IADDA(IX+d)
Set_IADDA(IY+d)
Set_IADCAn
Set_IADCA(IX+d)
Set_IADCA(IY+d)
Set_ISUBAn
Set_ISUBA(IX+d)
Set_ISUBA(IY+d)
Set_ISBCAn
Set_ISBCA(IX+d)
Set_ISBCA(IY+d)
Set_IANDn
Set_IAND(IX+d)
Set_IAND(IY+d)
Set_IORn
Set_IOR(IX+d)
Set_IOR(IY+d)
Set_IXORn
Set_IXOR(IX+d)
Set_IXOR(IY+d)
Set_ICPn
Set_ICP(IX+d)
Set_ICP(IY+d)
Set_IINC(IX+d)
Set_IINC(IY+d)
Set_IDEC(IX+d)
Set_IDEC(IY+d)
Set_IRLC(IX+d)_0/1
Set_IRLC(IY+d)_0/1
Set_IRL(IX+d)_0/1
Set_IRL(IY+d)_0/1
Set_IRRC(IX+d)_0/1
Set_IRRC(IY+d)_0/1
Set_IRR(IX+d)_0/1
Set_IRR(IY+d)_0/1
Set_ISLA(IX+d)_0/1
Set_ISLA(IY+d)_0/1
Set_ISRA(IX+d)_0/1
Set_ISRA(IY+d)_0/1
Set_ISRL(IX+d)_0/1
Set_ISRL(IY+d)_0/1
Set_IJPnn_0/1
Set_IJPccnn_0/1/2/3/4/5/6/7_0/1
Set_IJRe
Set_IJRCe
Set_IJRNCe
Set_IJRZe
Set_IJRNZe
Set_IDJNZe
Set_ICALLnn_0/1
Set_IINA(n)
Set_IOUT(n)A
Reset_ITABLE
その他
Reset_ALLUNOFFICIALFF: CRESET以外の非公式フリップフロップをオールクリアする
ALU (PA)
入力
Select_A_high
Select_F_high
Select_B_high
Select_C_high
Select_D_high
Select_E_high
Select_H_high
Select_L_high
Select_Dt_high
Select_Dtcs_high
Select_Din_high
Select_R_high
Select_I_high
Select_AF_high
Select_BC_high
Select_DE_high
Select_HL_high
Select_PC_high
Select_SP_high
Select_IX_high
Select_IY_high
Select_0x0_high
Select_0x1_high
Select_A_low
Select_F_low
Select_B_low
Select_C_low
Select_D_low
Select_E_low
Select_H_low
Select_L_low
Select_Dt_low
Select_Dtcs_low
Select_Din_low
Select_R_low
Select_I_low
Select_OP_low
Select_AF_low
Select_BC_low
Select_DE_low
Select_HL_low
Select_PC_low
Select_SP_low
Select_IX_low
Select_IY_low
Select_IOP_low
Select_OPOPold_low
Select_0xffOP_low
Select_0x0_low
Select_0x1_low
Select_0x8_low
Select_0x10_low
Select_0x18_low
Select_0x20_low
Select_0x28_low
Select_0x30_low
Select_0x38_low
Select_0x66_low
Select_0x99_low
Select_0x06_low
Select_0x60_low
Select_0x2_low
Select_0x4_low
Select_0x40_low
Select_0x80_low
演算
NOP
ADD
ADC
SUB
SBC
AND
NLAND
OR
XOR
NOT
RLC
RL
RRC
RR
SLA
SRA
SRL
RLD
RRD
インターフェース (PI)
トライステート
Activate_Ad_high
Activate_Ad_low
Activate_Dt
Nullify_MREQ
Nullify_RD
Nullify_WR
Nullify_IORQ
アドレスバス
SelectAd_PC
SelectAd_SP
SelectAd_BC
SelectAd_DE
SelectAd_IR
SelectAd_HL
SelectAd_DtexDt
SelectAd_OPOPold
SelectAd_ALU
SelectAd_AOP
データバス
SelectDt_PC_high
SelectDt_PC_low
SelectDt_IX_high
SelectDt_IX_low
SelectDt_IY_high
SelectDt_IY_low
SelectDt_A
SelectDt_F
SelectDt_B
SelectDt_C
SelectDt_D
SelectDt_E
SelectDt_H
SelectDt_L
SelectDt_OP
SelectDt_Dt
SelectDt_Dtex
その他
ReadDtcs: Dtcs←Din
SelectAd+1: アドレスバスを+1する
Flag_MREQ
Flag_RD
Flag_WR
Flag_RFSH
Flag_IORQ
Flag_M1
Flag_BUSACK
Flag_HALT
半遅延インターフェース (PhI)
Activate_Dt
Flag_MREQ
Flag_RD
Flag_WR
Flag_RFSH
Flag_IORQ
Flag_M1
Flag_BUSACK
遅延 (Pa)
Ophd (命令の先頭であることを表す)
ALU
演算
NOP
ADD
high + low
ADC
high + low + Frag_C
SUB
high + NOT(low) + 1
SBC
high + NOT(low) + !Frag_C
AND
NLAND
{ high }AND{ NOT(low) }
OR
XOR
NOT
RLC
[low_6,…,low_0,low_7]
RL
[low_6,…,low_0,Frag_C]
RRC
[low_0,low_7,…,low_1]
RR
[Frag_C,low_7,…,low_1]
SLA
[low_6,…,low_0,0]
SRA
[low_7,low_7,…,low_1]
SRL
[0,low_7,…,low_1]
RLD
low_0~3→high_0~3→high_4~7→low_0~3
RRD
low_0~3→high_4~7→high_0~3→low_0~3
出力バス
bit | |
---|---|
0~15 | 演算結果 |
(16) | 0 |
(17) | 1 |
(18) | IFF2{AND}CINT |
19 | is8bitEqual |
20 | is16bitEqual |
21 | HCY(4つめの全加算機から5つめへのcally) |
(22) | ハーフボロー not(HCY)のこと |
23 | CY(8つ目からのキャリー) |
24 | isResultLow0 |
25 | is8bitOverFlow |
(26) | ボロー |
27 | is8bitEvenParity |
28 | DAA_Frag_H |
(29) | Frag_S |
(30) | Frag_C |
31 | 16bitハーフキャリー(12から) |
32 | 16bitキャリー(16から) |
33 | is16bitOverFlow |
34 | isResult0 |
(35) | 16bitハーフボロー |
(36) | 16bitボロー |
37 | inputLow0 |
38 | inputLow7 |
(39) | - |
(40~45) | Not(演算結果) |
19 is8bitEqual
[low_0~7] == [high_0~7]
21 ハーフキャリー
4つ目の全加算器からのキャリー
22 ハーフボロー
!ハーフキャリー
25 is8bitOverFlow
high_7 | low_7 | result_7 | V |
---|---|---|---|
1 | 1 | 0 | 1 |
0 | 0 | 1 | 1 |
SUB/SBC はNOT処理をしたlowで比較する
27 is8bitEvenParity
result_0~7における bit1 の数が偶数
28 DAA_Frag_H
{ high_4 }XOR{ result_4 }
デコーダ
正しい書き方がわからないので... いまいち分かりにくいかもしれません。
標準サイクル
M1(4)
0 | M1 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 PI_Flag_MREQ PI_Flag_RD if(WAIT)→PA_Select_Din_low PA_NOP PR_Write_OP PI_SlideOP P2_Reset_CM1 if(/WAIT)→PR_Halt_XPT | |
cl↓ | |||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_IR PI_Flag_RFSH (PR_Inc_PC) | |
cl↓ | PhI_Flag_MREQ | ||
3 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_IR PI_Flag_RFSH PR_Inc_R | |
cl↓ |
MR (3)
0 | MR | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Read_Dtcs PR_SlideOP PA_Select_Dtcs_low PA_NOP PR_Write_OP P2_Reset_CMR if(!CINT0_CALL)→PR_Inc_PC | |
cl↓ |
MA (3)
0 | MR | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Read_Dtcs (PA_Select_???_high) PA_Select_Dtcs_low (PA_???) (PR_Write_???) (?PR_InvertIn) PR_Inc_PC P2_Reset_CMA | |
cl↓ |
R (3)
0 | R | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Read_Dtcs PA_Select_Dtcs_low PA_NOP (PR_Write_???) (?PR_InvertIn) | |
cl↓ |
RA (3)
0 | R | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_MREQ PhI_Flag_RD | ||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Read_Dtcs (PA_Select_???_high) PA_Select_Dtcs_low (PA_???) (PR_Write_???) (?PR_InvertIn) | |
cl↓ |
W (3)
0 | W | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) (PI_SelectDt_???) |
cl↓ | PhI_Flag_MREQ PhI_Activate_Dt | ||
1(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Activate_Dt (PI_SelectDt_???) if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_MREQ PhI_Flag_WR | ||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Activate_Dt (PI_Select_Dt_???) | |
cl↓ |
I (4)
0 | I | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) |
cl↓ | |||
1 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Flag_IORQ PI_Flag_RD | |
cl↓ | |||
2(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Flag_IORQ PI_Flag_RD if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_IORQ PhI_Flag_RD | ||
3 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Read_Dtcs PA_Select_Dtcs_low PA_NOP (PR_Write_???) (?PR_InvertIn) | |
cl↓ |
O (4)
0 | O | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) (PI_SelectDt_???) |
cl↓ | PhI_Activate_Dt | ||
1 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Activate_Dt (PI_SelectDt_???) PI_Flag_IORQ PI_Flag_WR | |
cl↓ | |||
2(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Activate_Dt (PI_SelectDt_???) PI_Flag_IORQ PI_Flag_WR if(/TWAIT)→PR_Halt_XPT | |
cl↓ | PhI_Flag_IORQ PhI_Flag_WR | ||
3 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low (PI_SelectAd_???) PI_Activate_Dt (PI_SelectDt_???) | |
cl↓ |
割り込みサイクル
マスク可能割り込み
IFF==1&&/TINT or CINT0,1,2
0 | cl↑ | P2_Set_CINT0/1/2 P2_Reset_LHALT P2_Reset_TINT P2_Reset_IFF1 P2_Reset_IFF2 PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 | |
cl↓ | |||
1 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 | |
cl↓ | |||
2 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 | |
cl↓ | PhI_Flag_IORQ | ||
3(W) | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_PC PI_Flag_M1 PI_Flag_IORQ if(WAIT)→PA_Select_Din_low PA_NOP PR_Write_OP if(/WAIT)→PR_Halt_XPT | |
cl↓ | |||
4 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_IR PI_Flag_RFSH | |
cl↓ | PhI_Flag_MREQ | ||
5 | cl↑ | PI_Activate_Ad_high PI_Activate_Ad_low PI_SelectAd_IR PI_Flag_RFSH PR_Inc_R if(CINT0)→PI_Reset_CINT if(OP=11 ppp 111)→PI_Set_CINT0_RST if(OP=11 001 101)→PI_Set_CINT0_CALL | |
cl↓ |
モード0 RST
CINT0_RST
6 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high PR_Dec_SP | |
cl↓ | |||
10 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low |
cl↓ | |||
11(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low | |
cl↓ | |||
12 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CINT PI_SelectAd_SP PI_SelectDt_PC_low PA_Select_0x0/8/10/18/20/28/30/38_low PA_NOP PR_Write_PC_high PR_Write_PC_low | |
cl↓ | |||
(E) | Pa_Ophd |
モード0 CALL
CINT0_CALL
6 | MR | cl↑ | |
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | MR | cl↑ | |
cl↓ | |||
10 | cl↑ | ||
cl↓ | |||
11 | cl↑ | ||
cl↓ | |||
12 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
13 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high |
cl↓ | |||
14(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high | |
cl↓ | |||
15 | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high PR_Dec_SP | |
cl↓ | |||
16 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low |
cl↓ | |||
17(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low | |
cl↓ | |||
18 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CINT PI_SelectAd_SP PI_SelectDt_PC_low PA_Select_OPOPold_low PA_NOP PR_Write_PC_high PR_Write_PC_low | |
cl↓ | |||
(E) | Pa_Ophd |
モード1
CINT1
6 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high PR_Dec_SP | |
cl↓ | |||
10 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low |
cl↓ | |||
11(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low | |
cl↓ | |||
12 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CINT PI_SelectAd_SP PI_SelectDt_PC_low PA_Select_0x38_low PA_NOP PR_Write_PC_high PR_Write_PC_low | |
cl↓ | |||
(E) | Pa_Ophd |
モード2
CINT2
6 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high PR_Dec_SP | |
cl↓ | |||
10 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low |
cl↓ | |||
11(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low | |
cl↓ | |||
12 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CINT PI_SelectAd_SP PI_SelectDt_PC_low PA_Select_IOP_low PA_NOP PR_Write_PC_high PR_Write_PC_low | |
cl↓ | |||
(E) | Pa_Ophd |
マスク不能割り込み
/TNMI or CNMI
0 | M1 | cl↑ | P2_Set_CNMI P2_Reset_TNMI P2_Reset_LHALT P2_EvacuateIFF P2_Reset_IFF1 |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high | |
cl↓ | |||
7 | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_high PR_Dec_SP | |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_PC_low | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CNMI PI_SelectAd_SP PI_SelectDt_PC_low PA_Select_0x66_low PA_NOP PR_Write_PC_high PR_Write_PC_low | |
cl↓ | |||
(E) | Pa_Ophd |
バス要求
/BUSRQ or CBUSRQ
0(W) | cl↑ | P2_Set_CBUSRQ PI_Nullify_MREQ PI_Nullify_RE PI_Nullify_WR PI_Nullify_IORQ PI_Flag_BUSACK if(/BUSRQ)PR_Halt_XPT | |
cl↓ | PhI_Flag_BUSACK | ||
1 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_CBUSRQ | |
cl↓ | |||
(E) | Pa_Ophd |
リセット
/TRSET&&/RESET
0 | cl↑ | ||
cl↓ |
/TRSET&&RESET
/TRSET&&RESET | cl↑ | P2_Set_CRESET P2_Reset_ALL_except_CRESET | |
cl↓ |
CRESET
CRESET | cl↑ | PR_Reset_XPT PA_Select_0x0 PA_NOP PR_Write_PC_low PR_Write_PC_high PR_Write_I PR_Write_R P2_Reset_CRESET P2_Set_CM1 P2_IM0 P2_Reset_IFF1 P2_Reset_IFF2 | |
cl↓ | |||
(E) | Pa_Ophd |
命令
X:命令長
M:Mサイクル数
T:Tサイクル数
r:レジスタ(8bit)
rrr/r’r’r’ | 対応レジスタ |
---|---|
000 | B |
001 | C |
010 | D |
011 | E |
100 | H |
101 | L |
111 | A |
dd:レジスタ(16bit)
dd | 対応レジスタ |
---|---|
00 | BC |
01 | DE |
10 | HL |
11 | SP |
qq:レジスタ(16bit)
対応レジスタ | |
---|---|
00 | BC |
01 | DE |
10 | HL |
11 | AF |
ss:レジスタ(16bit)
ss | 対応レジスタ |
---|---|
00 | BC |
01 | DE |
10 | HL |
11 | SP |
pp:レジスタ(16bit)
pp | 対応レジスタ |
---|---|
00 | BC |
01 | DE |
10 | IX |
11 | SP |
rr:レジスタ(16bit)
rr | 対応レジスタ |
---|---|
00 | BC |
01 | DE |
10 | IY |
11 | SP |
cc:条件
ccc | 条件 |
---|---|
000 | Z==0 |
001 | Z==1 |
010 | C==0 |
011 | C==1 |
100 | P==0 |
101 | P==1 |
110 | S==0 |
111 | S==1 |
p
ppp | 8*p |
---|---|
000 | 0x00 |
001 | 0x08 |
010 | 0x10 |
011 | 0x18 |
100 | 0x20 |
101 | 0x28 |
110 | 0x30 |
111 | 0x38 |
; 同時実行
* フラグ変更
8bitデータ移動
LD r,r’ (X1/M1/T4) [M1]
r←r’
命令
01 rrr r’r’r’
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PA_SELECT_A/B/C/D/E/H/L_low PA_NOP ?PR_InvertIn PR_Write_A/B/C/D/E/H/L PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
LD r,n (X2/M2/T7) [M1\MR]
r←n
命令
00 rrr 110
nn nnn nnn
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_CMR PR_Reset_XPT P2_Set_ILDrn_A/B/C/D/E/H/L | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CM1 ?PR_InvertIn PR_Write_A/B/C/D/E/H/L P2_Reset_ITABLE | |
cl↓ | |||
(E) | Pa_Ophd |
LD r,(HL) (X1/M2/T7) [M1+R]
r←(HL)
命令
01 rrr 110
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL ?PR_InvertIn PR_Write_A/B/C/D/E/H/L | |
cl↓ | |||
(E) | Pa_Ophd |
LD r,(IX+d) (X3/M5/T19) [M1\M1\MR+5+R]
r←(IX+d)
命令
11 011 101
01 rrr 110
dd ddd ddd
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILDr(IX+d)_A/B/C/D/E/H/L | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PR_Write_A/B/C/D/E/H/L ?PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD r,(IY+d) (X3/M5/T19) [M1\M1\MR+5+R]
r←(IY+d)
命令
11 111 101
01 rrr 110
dd ddd ddd
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILDr(IY+d)_A/B/C/D/E/H/L | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PR_Write_A/B/C/D/E/H/L ?PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD (HL),r (X1/M2/T7) [M1+W]
(HL)←r
命令
01 110 rrr
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | W | cl↑ | PI_SelectAd_HL PI_SelectDt_A/B/C/D/E/H/L |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
(E) | Pa_Ophd |
LD (IX+d),r (X3/M5/T19) [M1\M1\MR+5+W]
(IX+d)←r
命令
11 011 101
01 110 rrr
dd ddd ddd
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILD(IX+d)r_A/B/C/D/E/H/L | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
(E) | Pa_Ophd |
LD (IY+d),r (X3/M5/T19) [M1\M1\MR+5+W]
(IY+d)←r
命令
11 111 101
01 110 rrr
dd ddd ddd
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILD(IY+d)r_A/B/C/D/E/H/L | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PI_SelectDt_A/B/C/D/E/H/L | |
cl↓ | |||
(E) | Pa_Ophd |
LD (HL),n (X2/M3/T10) [M1\MR+W]
(HL)←n
命令
00 110 110
nn nnn nnn
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(HL)n | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_HL PI_SelectDt_OP |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_HL PI_SelectDt_OP | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_HL PI_SelectDt_OP | |
cl↓ | |||
(E) | Pa_Ophd |
LD (IX+d),n (X4/M5/T19) [M1\M1\MR\MR+2+W]
(IX+d)←n
命令
11 011 101
00 110 110
dd ddd ddd
nn nnn nnn
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILD(IX+d)n_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(IX+d)n_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 2 | cl↑ | PA_Select_IX_high PA_Select_OPold_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_OP |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_OP | |
cl↓ | |||
7 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PI_SelectDt_OP | |
cl↓ | |||
(E) | Pa_Ophd |
LD (IY+d),n (X4/M5/T19) [M1\M1\MR\MR+2+W]
(IY+d)←n
命令
11 111 101
00 110 110
dd ddd ddd
nn nnn nnn
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILD(IY+d)n_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(IY+d)n_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 2 | cl↑ | PA_Select_IY_high PA_Select_OPold_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_OP |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_DtexDt PI_SelectDt_OP | |
cl↓ | |||
7 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PI_SelectDt_OP | |
cl↓ | |||
(E) | Pa_Ophd |
LD A,(BC) (X1/M2/T7) [M1+R]
A←(BC)
命令
00 001 010
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_BC |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_BC | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_BC PR_Write_A PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD A,(DE) (X1/M2/T7) [M1+R]
A←(DE)
命令
00 011 010
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_DE |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_DE | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_DE PR_Write_A PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD A,(nn) (X3/M4/T13) [M1\MR\MR+R]
A←(nn)
命令
00 111 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDA(nn)_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDA(nn)_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | R | cl↑ | PI_SelectAd_OPOPold |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PR_Write_A PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD (BC),A (X1/M2/T7) [M1+W]
(BC)←A
命令
00 000 010
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | W | cl↑ | PI_SelectAd_BC PI_SelectDt_A |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_BC PI_SelectDt_A | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_BC PI_SelectDt_A | |
cl↓ | |||
(E) | Pa_Ophd |
LD (DE),A (X1/M2/T7) [M1+W]
(DE)←A
命令
00 010 010
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | W | cl↑ | PI_SelectAd_DE PI_SelectDt_A |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_DE PI_SelectDt_A | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_DE PI_SelectDt_A | |
cl↓ | |||
(E) | Pa_Ophd |
LD (nn),A (X3/M4/T13) [M1\MR\MR+W]
(nn)←A
命令
00 110 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_ILD(nn)A_0 PR_Reset_XPT P2_Set_CMR | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Set_ILD(nn)A_1 PR_Reset_XPT P2_Set_CMR | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_A |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_A | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectDt_A | |
cl↓ | |||
(E) | Pa_Ophd |
*LD A,I (X2/M2/T9) [M1\M1+1]
A←I
命令
11 101 101
01 010 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
I==0 | IFF2 | I<0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_I_low PA_NOP PR_Write_A PR_InvertIn PF_Write_Z PF_Select_Z_bit19 PF_Write_P/V PF_Select_P/V_bit18 PF_Write_S PF_Select_S_bit7 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
(E) | Pa_Ophd |
*LD A,R (X2/M2/T9) [M1\M1+1]
A←R
命令
11 101 101
01 011 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
R==0 | IFF2 | R<0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_R_low PA_NOP PR_Write_A PR_InvertIn PF_Write_Z PF_Select_Z_bit19 PF_Write_P/V PF_Select_P/V_bit18 PF_Write_S PF_Select_S_bit7 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
(E) | Pa_Ophd |
LD I,A (X2/M2/T9) [M1\M1+1]
I←A
命令
11 101 101
01 000 111
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_A_low PA_NOP PR_Write_I PR_InvertIn |
cl↓ | |||
(E) | Pa_Ophd |
LD R,A (X2/M2/T9) [M1\M1+1]
R←A
命令
11 101 101
01 001 111
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_A_low PA_NOP PR_Write_R |
cl↓ | |||
(E) | Pa_Ophd |
16bitデータ移動
LD dd,nn (X3/M3/T10) [M1\MR\MR]
dd←nn
命令
00 dd0 001
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_BC/DE/HL/SP_ILDddnn_0 P2_Set_CMR | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Set_BC/DE/HL/SP_ILDddnn_1 P2_Set_CMR PR_Write_C/E/L/SP_low | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PR_Write_B/D/H/SP_high PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD IX,nn (X4/M4/T14) [M1\M1\MR\MR]
IX←nn
命令
11 011 101
00 100 001
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILDIXnn_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Set_ILDIXnn_1 P2_Set_CMR PR_Write_IX_low | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PR_Write_IX_high | |
cl↓ | |||
(E) | Pa_Ophd |
LD IY,nn (X4/M4/T14) [M1\M1\MR\MR]
IY←nn
命令
11 111 101
00 100 001
nn nnn nnn (low)
nn nnn nnn (high)\
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILDIYnn_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Set_ILDIYnn_1 P2_Set_CMR PR_Write_IY_low | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PR_Write_IY_high | |
cl↓ | |||
(E) | Pa_Ophd |
LD HL,(nn) (X3/M5/T16) [M1\MR\MR+R+R]
L←(nn)
H←(nn+1)
命令
00 101 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDHL(nn)_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDHL(nn)_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | R | cl↑ | PI_SelectAd_OPOPold |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PR_Write_L | |
cl↓ | |||
6 | R | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PR_Write_H PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD dd,(nn) (X4/M6/T20) [M1\M1\MR\MR+R+R]
dd_low←(nn)
dd_high←(nn+1)
命令
11 101 101
01 dd1 011
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XOTR P2_Set_ILDdd(nn)_BC/DE/HL/SP_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDdd(nn)_BC/DE/HL/SP_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | R | cl↑ | PI_SelectAd_OPOPold |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PR_Write_C/E/L/SP_low | |
cl↓ | |||
6 | R | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PR_Write_B/D/H/SP_high PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD IX,(nn) (X4/M6/T20) [M1\M1\MR\MR+R+R]
IX_low←(nn)
IX_high←(nn+1)
命令
11 011 101
00 101 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILDIX(nn)_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDIX(nn)_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | R | cl↑ | PI_SelectAd_OPOPold |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PR_Write_IX_low | |
cl↓ | |||
6 | R | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PR_Write_IX_high PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD IY,(nn) (X4/M6/T20) [M1\M1\MR\MR+R+R]
IY_low←(nn)
IY_high←(nn+1)
命令
11 111 101
00 101 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILDIY(nn)_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILDIY(nn)_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | R | cl↑ | PI_SelectAd_OPOPold |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PR_Write_IY_low | |
cl↓ | |||
6 | R | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PR_Write_IY_high PR_InvertIn | |
cl↓ | |||
(E) | Pa_Ophd |
LD (nn),HL (X3/M5/T16) [M1\MR\MR+W+W]
(nn)←L
(nn+1)←H
命令
00 100 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(nn)HL_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(nn)HL_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_L |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_L | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_L | |
cl↓ | |||
6 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_H |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_H | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_H | |
cl↓ | |||
(E) | Pa_Ophd |
LD (nn),dd (X4/M6/T20) [M1\M1\MR\MR+W+W]
(nn)←dd_low
(nn+1)←dd_high
命令
11 101 101
01 dd0 011
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XOTR P2_Set_ILD(nn)dd_BC/DE/HL/SP_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(nn)dd_BC/DE/HL/SP_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_C/E/L/SP_low |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_C/E/L/SP_low | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_C/E/L/SP_low | |
cl↓ | |||
6 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_B/D/H/SP_high |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_B/D/H/SP_high | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_B/D/H/SP_high | |
cl↓ | |||
(E) | Pa_Ophd |
LD (nn),IX (X4/M6/T20) [M1\M1\MR\MR+W+W]
(nn)←IX_low
(nn+1)←IX_high
命令
11 011 101
00 100 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ILD(nn)IX_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(nn)IX_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IX_low |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IX_low | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IX_low | |
cl↓ | |||
6 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IX_high |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IX_high | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IX_high | |
cl↓ | |||
(E) | Pa_Ophd |
LD (nn),IY (X4/M6/T20) [M1\M1\MR\MR+W+W]
(nn)←IY_low
(nn+1)←IY_high
命令
11 111 101
00 100 010
nn nnn nnn (low)
nn nnn nnn (high)
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ILD(nn)IY_0 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Set_ILD(nn)IY_1 | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IY_low |
cl↓ | |||
4(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IY_low | |
cl↓ | |||
5 | cl↑ | PI_SelectAd_OPOPold PI_SelectDt_IY_low | |
cl↓ | |||
6 | W | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IY_high |
cl↓ | |||
7(W) | cl↑ | PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IY_high | |
cl↓ | |||
8 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_OPOPold PI_SelectAd+1 PI_SelectDt_IY_high | |
cl↓ | |||
(E) | Pa_Ophd |
LD SP,HL (X1/M1/T6) [M1+2]
SP←HL
命令
11 111 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_HL_low PA_NOP PR_Write_SP | |
cl↓ | |||
(E) | Pa_Ophd |
LD SP,IX (X2/M2/T10) [M1\M1+2]
SP←IX
命令
11 011 101
11 111 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX PA_Select_IX_low PA_NOP PR_Write_SP | |
cl↓ | |||
(E) | Pa_Ophd |
LD SP,IY (X2/M2/T10) [M1\M1+2]
SP←IY
命令
11 111 101
11 111 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY PA_Select_IY_low PA_NOP PR_Write_SP | |
cl↓ | |||
(E) | Pa_Ophd |
PUSH qq (X1/M3/T11) [M1+1+W+W]
SP←SP-1
(SP)←qq_high
SP←SP-1
(SP)←qq_low
命令
11 qq0 101
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_B/D/H/A |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_B/D/H/A | |
cl↓ | |||
7 | cl↑ | PI_SelectAd_SP PI_SelectDt_B/D/H/A PR_Dec_SP | |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_C/E/L/F |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_C/E/L/F | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_SP PI_SelectDt_C/E/L/F | |
cl↓ | |||
(E) | Pa_Ophd |
PUSH IX (X2/M4/T15) [M1\M1+1+W+W]
SP←SP-1
(SP)←IX_high
SP←SP-1
(SP)←IX_low
命令
11 011 101
11 100 101
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_IX_high |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_IX_high | |
cl↓ | |||
7 | cl↑ | PI_SelectAd_SP PI_SelectDt_IX_high PR_Dec_SP | |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_IX_low |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_IX_low | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Reset_XIX P2_Set_CM1 PI_SelectAd_SP PI_SelectDt_IX_low | |
cl↓ | |||
(E) | Pa_Ophd |
PUSH IY (X2/M4/T15) [M1\M1+1+W+W]
SP←SP-1
(SP)←IY_high
SP←SP-1
(SP)←IY_low
命令
11 111 101
11 100 101
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 1 | cl↑ | PR_Dec_SP |
cl↓ | |||
5 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_IY_high |
cl↓ | |||
6(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_IY_high | |
cl↓ | |||
7 | cl↑ | PI_SelectAd_SP PI_SelectDt_IY_high PR_Dec_SP | |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_IY_low |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_IY_low | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Reset_XIY P2_Set_CM1 PI_SelectAd_SP PI_SelectDt_IY_low | |
cl↓ | |||
(E) | Pa_Ophd |
POP qq (X1/M3/T10) [M1+R+R]
qq_low←(SP)
SP←SP+1
qq_high←(SP)
SP←SP+1
命令
11 qq0 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Inc_SP PR_Write_C/E/L/F | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
9 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_SP PR_Inc_SP PR_Write_B/D/H/A PR_InverIn | |
cl↓ | |||
(E) | Pa_Ophd |
POP IX (X2/M4/T14) [M1\M1+R+R]
IX_low←(SP)
SP←SP+1
IX_high←(SP)
SP←SP+1
命令
11 011 101
11 100 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Inc_SP PR_Write_IX_low | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
9 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX PI_SelectAd_SP PR_Inc_SP PR_Write_IX_high PR_InverIn | |
cl↓ | |||
(E) | Pa_Ophd |
POP IY (X2/M4/T14) [M1\M1+R+R]
IY_low←(SP)
SP←SP+1
IY_high←(SP)
SP←SP+1
命令
11 111 101
11 100 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Inc_SP PR_Write_IY_low | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
9 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY PI_SelectAd_SP PR_Inc_SP PR_Write_IY_high PR_InverIn | |
cl↓ | |||
(E) | Pa_Ophd |
交換・ブロック転送および検索
EX DE,HL (X1/M1/T4) [M1]
DE↔HL
命令
11 101 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PR_Ex_DE_HL | |
cl↓ | |||
(E) | Pa_Ophd |
EX AF,A’F’ (X1/M1/T4) [M1]
AF↔A’F’
命令
00 001 000
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PR_Ex_AF_A’F’ | |
cl↓ | |||
(E) | Pa_Ophd |
EXX (X1/M1/T4) [M1]
BC↔B’C’
DE↔D’E’
HL↔H’L’
命令
11 011 001
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PR_Exx | |
cl↓ | |||
(E) | Pa_Ophd |
EX (SP),HL (X1/M5/T19) [M1+R+R+1+W+W+2]
L↔(SP)
H↔(SP+1)
命令
11 100 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PA_Select_HL_low PA_NOP PR_Write_Dt PR_Write_Dtex | |
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Write_L | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP PI_SelectAd+1 |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PR_Write_H PR_InvertIn | |
cl↓ | |||
10 | 1 | cl↑ | |
cl↓ | |||
11 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt |
cl↓ | |||
12(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
13 | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
14 | W | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex |
cl↓ | |||
15(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
16 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
17 | 2 | cl↑ | |
cl↓ | |||
18 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
EX (SP),IX (X2/M6/T23) [M1\M1+R+R+1+W+W+2]
IX_low↔(SP)
IX_high↔(SP+1)
命令
11 011 101
11 100 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PA_Select_IX_low PA_NOP PR_Write_Dt PR_Write_Dtex | |
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Write_IX_low | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP PI_SelectAd+1 |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PR_Write_IX_high PR_InvertIn | |
cl↓ | |||
10 | 1 | cl↑ | |
cl↓ | |||
11 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt |
cl↓ | |||
12(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
13 | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
14 | W | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex |
cl↓ | |||
15(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
16 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
17 | 2 | cl↑ | |
cl↓ | |||
18 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX | |
cl↓ | |||
(E) | Pa_Ophd |
EX (SP),IY (X2/M6/T23) [M1\M1+R+R+1+W+W+2]
IY_low↔(SP)
IY_high↔(SP+1)
命令
11 111 101
11 100 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PA_Select_IY_low PA_NOP PR_Write_Dt PR_Write_Dtex | |
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_SP |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_SP | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_SP PR_Write_IY_low | |
cl↓ | |||
7 | R | cl↑ | PI_SelectAd_SP PI_SelectAd+1 |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PR_Write_IY_high PR_InvertIn | |
cl↓ | |||
10 | 1 | cl↑ | |
cl↓ | |||
11 | W | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt |
cl↓ | |||
12(W) | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
13 | cl↑ | PI_SelectAd_SP PI_SelectDt_Dt | |
cl↓ | |||
14 | W | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex |
cl↓ | |||
15(W) | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
16 | cl↑ | PI_SelectAd_SP PI_SelectAd+1 PI_SelectDt_Dtex | |
cl↓ | |||
17 | 2 | cl↑ | |
cl↓ | |||
18 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY | |
cl↓ | |||
(E) | Pa_Ophd |
*LDI (X2/M4/T16) [M1\M1+R+W+2]
(DE)←(HL)
DE←DE+1
BC←BC-1
HL←HL+1
命令
11 101 101
10 100 000
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
BC - 1 != 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt PA_Select_DE_low PA_Select_0x1_high PA_ADD PR_Write_D PR_Write_E | |
cl↓ | |||
10 | 2 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
11 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_HL_low PA_Select_0x1_high PA_ADD PR_Write_H PR_Write_L | |
cl↓ | |||
(E) | Pa_Ophd |
*LDIR (X2/M5/T21)/(X2/M4/T16) [M1\M1+R+W+7/2]
BC -1 == 0のときはT16
(DE)←(HL)
DE←DE+1
BC←BC-1
HL←HL+1
BC != 0 ⇒ PC←PC-2
命令
11 101 101
10 110 000
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
BC - 1 != 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt PA_Select_DE_low PA_Select_0x1_high PA_ADD PR_Write_D PR_Write_E | |
cl↓ | |||
10 | 2 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
11 | cl↑ | PA_Select_HL_low PA_Select_0x1_high PA_ADD PR_Write_H PR_Write_L if(!Flag_P/V)→PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | if(!Flag_P/V)→Pa_Ophd |
12 | 5 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low |
cl↓ | |||
13 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low | |
cl↓ | |||
14 | cl↑ | ||
cl↓ | |||
15 | cl↑ | ||
cl↓ | |||
16 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*LDD (X2/M4/T16) [M1\M1+R+W+2]
(DE)←(HL)
DE←DE-1
BC←BC-1
HL←HL-1
命令
11 101 101
10 101 000
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
BC - 1 != 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt PA_Select_DE_high PA_Select_0x1_low PA_SUB PR_Write_D PR_Write_E | |
cl↓ | |||
10 | 2 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
11 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_HL_high PA_Select_0x1_low PA_SUB PR_Write_H PR_Write_L | |
cl↓ | |||
(E) | Pa_Ophd |
*LDDR (X2/M5/T21)/(X2/M4/T16) [M1\M1+R+W+7/2]
BC -1 == 0のときはT16
(DE)←(HL)
DE←DE-1
BC←BC-1
HL←HL-1
BC != 0 ⇒ PC←PC-2
命令
11 101 101
10 111 000
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
BC - 1 != 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | W | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt |
cl↓ | |||
8(W) | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt | |
cl↓ | |||
9 | cl↑ | PI_SelectAd_DE PI_SelectDt_Dt PA_Select_DE_high PA_Select_0x1_low PA_SUB PR_Write_D PR_Write_E | |
cl↓ | |||
10 | 2 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 |
cl↓ | |||
11 | cl↑ | PA_Select_HL_high PA_Select_0x1_low PA_SUB PR_Write_H PR_Write_L if(!Flag_P/V)→PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | if(!Flag_P/V)→Pa_Ophd |
12 | 5 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low |
cl↓ | |||
13 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low | |
cl↓ | |||
14 | cl↑ | ||
cl↓ | |||
15 | cl↑ | ||
cl↓ | |||
16 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*CPI (X2/M4/T16) [M1\M1+R+5]
A-(HL) (するだけ)
BC←BC-1
HL←HL+1
命令
11 101 101
10 100 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A == (HL) | BC - 1 != 0 | A-(HL) < 0 | 1 | A-(HL)のハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt PR_InvertIn | |
cl↓ | |||
7 | 5 | cl↑ | PA_Select_A_high PA_Select_Dt_low PA_SUB PF_Write_Z PF_Select_Z_bit19 PF_Write_S PF_Select_S_bit7 PF_Write_H PF_Select_H_bit22 |
cl↓ | |||
8 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 | |
cl↓ | |||
9 | cl↑ | PA_Select_HL_high PA_Select_0x1_low PA_ADD PR_Write_H PR_Write_L PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
10 | cl↑ | ||
cl↓ | |||
11 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*CPIR (X2/M5/T21)/(X2/M4/T16) [M1\M1+R+10/5]
A == (HL) or BC-1 == 0のときT16
A-(HL) (するだけ)
HL←HL+1
BC←BC-1
BC != 0 ⇒ PC←PC-2
命令
11 101 101
10 110 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A == (HL) | BC - 1 != 0 | A-(HL) < 0 | 1 | A-(HL)のハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt PR_InvertIn | |
cl↓ | |||
7 | 5 | cl↑ | PA_Select_A_high PA_Select_Dt_low PA_SUB PF_Write_Z PF_Select_Z_bit19 PF_Write_S PF_Select_S_bit7 PF_Write_H PF_Select_H_bit22 |
cl↓ | |||
8 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 | |
cl↓ | |||
9 | cl↑ | PA_Select_HL_high PA_Select_0x1_low PA_ADD PR_Write_H PR_Write_L PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
10 | cl↑ | ||
cl↓ | |||
11 | cl↑ | if(!Flag_P/V or Flag_Z)→PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | if(!Flag_P/V or Flag_Z)→Pa_Ophd |
12 | 5 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low |
cl↓ | |||
13 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low | |
cl↓ | |||
14 | cl↑ | ||
cl↓ | |||
15 | cl↑ | ||
cl↓ | |||
16 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*CPD (X2/M4/T16) [M1\M1+R+5]
A-(HL) (するだけ)
BC←BC-1
HL←HL-1
命令
11 101 101
10 101 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A == (HL) | BC - 1 != 0 | A-(HL) < 0 | 1 | A-(HL)のハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt PR_InvertIn | |
cl↓ | |||
7 | 5 | cl↑ | PA_Select_A_high PA_Select_Dt_low PA_SUB PF_Write_Z PF_Select_Z_bit19 PF_Write_S PF_Select_S_bit7 PF_Write_H PF_Select_H_bit22 |
cl↓ | |||
8 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 | |
cl↓ | |||
9 | cl↑ | PA_Select_HL_high PA_Select_0x1_low PA_SUB PR_Write_H PR_Write_L PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
10 | cl↑ | ||
cl↓ | |||
11 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*CPDR (X2/M5/T21)/(X2/M4/T16) [M1\M1+R+10/5]
A==(HL) or BC-1 == 0のときT16
A-(HL) (するだけ)
BC←BC-1
HL←HL-1
BC != 0 ⇒ PC←PC-2
命令
11 101 101
10 111 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A == (HL) | BC - 1 != 0 | A-(HL) < 0 | 1 | A-(HL)のハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt PR_InvertIn | |
cl↓ | |||
7 | 5 | cl↑ | PA_Select_A_high PA_Select_Dt_low PA_SUB PF_Write_Z PF_Select_Z_bit19 PF_Write_S PF_Select_S_bit7 PF_Write_H PF_Select_H_bit22 |
cl↓ | |||
8 | cl↑ | PA_Select_BC_high PA_Select_0x1_low PA_SUB PR_Write_B PR_Write_C PF_Write_P/V PF_Select_P/V_bit20 | |
cl↓ | |||
9 | cl↑ | PA_Select_HL_high PA_Select_0x1_low PA_SUB PR_Write_H PR_Write_L PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
10 | cl↑ | ||
cl↓ | |||
11 | cl↑ | if(!Flag_P/V or Flag_Z)→PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | if(!Flag_P/V or Flag_Z)→Pa_Ophd |
12 | 5 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low |
cl↓ | |||
13 | cl↑ | PA_Select_PC_high PA_Select_0x1_low PA_SUB Write_PC_high Write_PC_low | |
cl↓ | |||
14 | cl↑ | ||
cl↓ | |||
15 | cl↑ | ||
cl↓ | |||
16 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
8bit算術・論理演算
*ADD A,r (X1/M1/T4) [M1]
A←A+r
命令
10 000 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+r = 0 | V | A+r < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD A,n (X2/M2/T7) [M1\MA]
A←A+n
命令
11 000 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+n = 0 | V | A+n < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_IADDAn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD A,(HL) (X1/M2/T7) [M1+RA]
A←A+(HL)
命令
10 000 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(HL) = 0 | V | A+(HL) < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD A,(IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A+(IX+d)
命令
11 011 101
10 000 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(IX+d) = 0 | V | A+(IX+d) < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IADDA(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD A,(IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A+(IY+d)
命令
11 111 101
10 000 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(IY+d) = 0 | V | A+(IY+d) < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IADDA(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC A,r (X1/M1/T4) [M1]
A←A+r+Frag_C
命令
10 001 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+r+Frag_C = 0 | V | A+r+Frag_C < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_ADC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC A,n (X2/M2/T7) [M1\MA]
A←A+n+Frag_C
命令
11 001 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+n+Frag_C = 0 | V | A+n+Frag_C < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_IADCAn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_ADC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC A,(HL) (X1/M2/T7) [M1+RA]
A←A+(HL)+Frag_C
命令
10 001 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(HL)+Frag_C = 0 | V | A+(HL)+Frag_C < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_ADC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC A,(IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A+(IX+d)+Frag_C
命令
11 011 101
10 001 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(IX+d)+Frag_C = 0 | V | A+(IX+d)+Frag_C < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IADCA(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt<br/PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC A,(IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A+(IY+d)+Frag_C
命令
11 111 101
10 001 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
キャリー | A+(IY+d)+Frag_C = 0 | V | A+(IY+d)+Frag_C < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IADCA(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit23 | |
cl↓ | |||
(E) | Pa_Ophd |
*SUB r (X1/M1/T4) [M1]
A←A-r
命令
10 010 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-r = 0 | V | A-r < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_SUB PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SUB n (X2/M2/T7) [M1\MA]
A←A-n
命令
11 010 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-n = 0 | V | A-n < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_ISUBAn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_SUB PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SUB (HL) (X1/M2/T7) [M1+RA]
A←A-(HL)
命令
10 010 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(HL) = 0 | V | A-(HL) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_SUB PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SUB (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A-(IX+d)
命令
11 011 101
10 010 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IX+d) = 0 | V | A-(IX+d) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ISUBA(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SUB PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SUB (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A-(IY+d)
命令
11 111 101
10 010 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IY+d) = 0 | V | A-(IY+d) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ISUBA(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SUB PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC r (X1/M1/T4) [M1]
A←A-r-Frag_C
命令
10 011 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-r-Frag_C = 0 | V | A-r-Frag_C < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_SBC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC n (X2/M2/T7) [M1\MA]
A←A-n-Frag_C
命令
11 011 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-n-Frag_C = 0 | V | A-n-Frag_C < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_ISBCAn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_SBC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC (HL) (X1/M2/T7) [M1+RA]
A←A-(HL)-Frag_C
命令
10 011 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(HL)-Frag_C = 0 | V | A-(HL)-Frag_C < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_SBC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A-(IX+d)-Frag_C
命令
11 011 101
10 011 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IX+d)-Frag_C = 0 | V | A-(IX+d)-Frag_C < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ISBCA(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SBC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A-(IY+d)-Frag_C
命令
11 111 101
10 011 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IY+d)-Frag_C = 0 | V | A-(IY+d)-Frag_C < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ISBCA(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SBC PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*AND r (X1/M1/T4) [M1]
A←A&r
命令
10 100 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A&r = 0 | P | A&r < 0 | 0 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_AND PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit17 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*AND n (X2/M2/T7) [M1\MA]
A←A&n
命令
11 100 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A&n = 0 | P | A&n < 0 | 0 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_IANDn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_AND PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit17 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*AND (HL) (X1/M2/T7) [M1+RA]
A←A&(HL)
命令
10 100 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A&(HL) = 0 | P | A&(HL) < 0 | 0 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit17 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*AND (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A&(IX+d)
命令
11 011 101
10 100 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A&(IX+d) = 0 | P | A&(IX+d) < 0 | 0 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IAND(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_AND PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit17 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*AND (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A&(IY+d)
命令
11 111 101
10 100 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A&(IY+d) = 0 | P | A&(IY+d) < 0 | 0 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IAND(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_AND PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_ADD PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit17 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*OR r (X1/M1/T4) [M1]
A←A|r
命令
10 110 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A|r = 0 | P | A|r < 0 | 0 | 0 |
0 | M1 | cl↑ | |
---|---|---|---|
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_OR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*OR n (X2/M2/T7) [M1\MA]
A←A|n
命令
11 110 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A|n = 0 | P | A|n < 0 | 0 | 0 |
0 | M1 | cl↑ | |
---|---|---|---|
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_IORn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_OR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*OR (HL) (X1/M2/T7) [M1+RA]
A←A|(HL)
命令
10 110 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A|(HL) = 0 | P | A|(HL) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_OR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*OR (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A|(IX+d)
命令
11 011 101
10 110 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A|(IX+d) = 0 | P | A|(IX+d) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IOR(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_OR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*OR (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A|(IY+d)
命令
11 111 101
10 110 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A|(IY+d) = 0 | P | A|(IY+d) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IOR(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_AND PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_OR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*XOR r (X1/M1/T4) [M1]
A←A^r命令
10 101 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A^r = 0 | P | A^r < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_XOR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*XOR n (X2/M2/T7) [M1\MA]
A←A^n
命令
11 101 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A^n = 0 | P | A^n < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_IXORn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_XOR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*XOR (HL) (X1/M2/T7) [M1+RA]
A←A^(HL)
命令
10 101 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A^(HL) = 0 | P | A^(HL) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_XOR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*XOR (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A^(IX+d)
命令
11 011 101
10 101 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A^(IX+d) = 0 | P | A^(IX+d) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IXOR(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_XOR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*XOR (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A←A^(IY+d)
命令
11 111 101
10 101 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
0 | A^(IY+d) = 0 | P | A^(IY+d) < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IXOR(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_AND PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_XOR PR_Write_A PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit16 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*CP r (X1/M1/T4) [M1]
A-r (するだけ)
命令
10 111 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-r = 0 | V | A-r < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_Select_A/B/C/D/E/H/L_low PA_SUB PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*CP n (X2/M2/T7) [M1\MA]
A-n
命令
11 111 110
nn nnn nnn
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-n = 0 | V | A-n < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | P2_Set_ICPn PR_Reset_XPT P2_Set_CMA | |
cl↓ | |||
0 | MA | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Reset_ITABLE PR_Reset_XPT P2_Set_CM1 PA_Select_A_high PA_SUB PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*CP (HL) (X1/M2/T7) [M1+RA]
A-(HL)
命令
10 111 110
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(HL) = 0 | V | A-(HL) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | RA | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PA_Select_A_high PA_SUB PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*CP (IX+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A-(IX+d)
命令
11 011 101
10 111 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IX+d) = 0 | V | A-(IX+d) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_ICP(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SUB PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*CP (IY+d) (X3/M5/T19) [M1\M1\MR+5+RA]
A-(IY+d)
命令
11 111 101
10 111 110
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | A-(IY+d) = 0 | V | A-(IY+d) < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_ICP(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | RA | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PI_SelectAd_DtexDt PA_Select_A_high PA_SUB PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 PF_Write_C PF_Select_C_bit26 | |
cl↓ | |||
(E) | Pa_Ophd |
*INC r (X1/M1/T4) [M1]
r←r+1
命令
00 rrr 100
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
r+1 = 0 | V | r+1 < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A/B/C/D/E/H/L_high PA_Select_0x1_low PA_ADD PR_Write_A/B/C/D/E/H/L ?PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*INC (HL) (X1/M3/T11) [M1+R+1+W]
(HL)←(HL)+1命令
00 110 100
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(HL)+1 = 0 | V | (HL)+1 < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_ADD PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_HL PI_SelectDt_Dt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_HL PI_SelectDt_Dt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
*INC (IX+d) (X3/M6/T23) [M1\M1\MR+5+R+1+W]
(IX+d)←(IX+d)+1
命令
11 011 101
00 110 100
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(IX+d)+1 = 0 | V | (IX+d)+1 < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IINC(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PI_SelectAd_DtexDt PR_Write_Dt | |
cl↓ | |||
11 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_ADD PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 |
cl↓ | |||
12 | W | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt |
cl↓ | |||
13(W) | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
14 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
*INC (IY+d) (X3/M6/T23) [M1\M1\MR+5+R+1+W]
(IY+d)←(IY+d)+1
命令
11 111 101
00 110 100
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(IY+d)+1 = 0 | V | (IY+d)+1 < 0 | 0 | ハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IINC(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PI_SelectAd_DtexDt PR_Write_Dt | |
cl↓ | |||
11 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_ADD PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit21 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit16 |
cl↓ | |||
12 | W | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt |
cl↓ | |||
13(W) | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
14 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
*DEC r (X1/M1/T4) [M1]
r←r-1
命令
00 rrr 101
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
r-1 = 0 | V | r-1 < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A/B/C/D/E/H/L_high PA_Select_0x1_low PA_SUB PR_Write_A/B/C/D/E/H/L ?PR_InvertIn PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
(E) | Pa_Ophd |
*DEC (HL) (X1/M3/T11) [M1+R+1+W]
(HL)←(HL)-1
命令
00 110 101
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(HL)-1 = 0 | V | (HL)-1 < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | R | cl↑ | PI_SelectAd_HL |
cl↓ | |||
5(W) | cl↑ | PI_SelectAd_HL | |
cl↓ | |||
6 | cl↑ | PI_SelectAd_HL PR_Write_Dt | |
cl↓ | |||
7 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_SUB PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 |
cl↓ | |||
8 | W | cl↑ | PI_SelectAd_HL PI_SelectDt_Dt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_HL PI_SelectDt_Dt | |
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 PI_SelectAd_HL PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
*DEC (IX+d) (X3/M6/T23) [M1\M1\MR+5+R+1+W]
(IX+d)←(IX+d)-1
命令
11 011 101
00 110 101
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(IX+d)-1 = 0 | V | (IX+d)-1 < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIX P2_Set_IDEC(IX+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PI_SelectAd_DtexDt PR_Write_Dt | |
cl↓ | |||
11 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_SUB PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit24 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 |
cl↓ | |||
12 | W | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt |
cl↓ | |||
13(W) | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
14 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PA_Select_IX_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
*DEC (IY+d) (X3/M6/T23) [M1\M1\MR+5+R+1+W]
(IY+d)←(IY+d)-1
命令
11 111 101
00 110 101
dd ddd ddd
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
(IY+d)-1 = 0 | V | (IY+d)-1 < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CMR P2_Reset_XIY P2_Set_IDEC(IY+d) | |
cl↓ | |||
0 | MR | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | ||
cl↓ | |||
3 | 5 | cl↑ | PA_Select_IX_high PA_Select_OP_low PA_ADD PR_Write_Dt PR_Write_Dtex |
cl↓ | |||
4 | cl↑ | ||
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | R | cl↑ | PI_SelectAd_DtexDt |
cl↓ | |||
9(W) | cl↑ | PI_SelectAd_DtexDt | |
cl↓ | |||
10 | cl↑ | PI_SelectAd_DtexDt PR_Write_Dt | |
cl↓ | |||
11 | 1 | cl↑ | PA_Select_Dt_high PA_Select_0x1_low PA_SUB PR_Write_Dt PF_Write_S PF_Select_S_bit7 PF_Write_Z PF_Select_Z_bit2 PF_Write_H PF_Select_H_bit22 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_N PF_Select_N_bit17 |
cl↓ | |||
12 | W | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt |
cl↓ | |||
13(W) | cl↑ | PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
14 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_ITABLE PA_Select_IY_high PA_Select_OP_low PA_ADD PI_SelectAd_ALU PI_SelectDt_Dt | |
cl↓ | |||
(E) | Pa_Ophd |
汎用算術演算およびCPU制御
*DAA (X1/M1/T4) [M1]*DAA (X1/M1/T4) [M1]
A←A.toDec()
詳しく書くと、
if(Frag_N)→
def m0x6 = (Frag_H or Aの下4bitが9より大きい)
def m0x60 = (Frag_C or Aが0x99より大きい)
switch((m0x6,m0x60)){
(1,1) A.toDec() = A - 0x66
(1,0) A.toDec() = A - 0x6
(0,0) A.toDec() = A
(0,1) A.toDec() = A -0x60
}
if(!Frag_N)→
def p0x6 = (Frag_H or Aの下4bitが9より大きい)
def p0x60 = (Frag_C or Aが0x99より大きい)
switch((m0x6,m0x60)){
(1,1) A.toDec() = A + 0x66
(1,0) A.toDec() = A + 0x6
(0,0) A.toDec() = A
(0,1) A.toDec() = A + 0x60
}\
命令
00 100 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
Aが0x99より大きい | A.toDec()=0 | P | A.toDec()<0 | A_4 XOR A.toDec()_4 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC PA_Select_A_high PA_Select_0x99_low PA_SUB PF_Write_S PF_Select_S_bit23 PF_Write_Z PF_Select_Z_bit21 | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 if(Frag_N)→PA_SUB if(!Frag_N)→PA_ADD PR_Write_A PR_InvertIn if((Frag_H or Frag_Z) and (Frag_C or Frag_S))→PA_Select_0x66_low if((Frag_H or Frag_Z) and !(Frag_C or Frag_S))→PA_Select_0x06_low if(!(Frag_H or Frag_Z) and (Frag_C or Frag_S))→PA_Select_0x60_low if(!(Frag_H or Frag_Z) and !(Frag_C or Frag_S))→PA_Select_0x0_low PF_Write_C PF_Select_C_bit29 PF_Write_Z PF_Select_Z_bit24 PF_Write_P/V PF_Select_P/V_bit27 PF_Write_S PF_Select_S_bit7 PF_Write_H PF_Select_H_bit28 | |
cl↓ | |||
(E) | Pa_Ophd |
*CPL (X1/M1/T4) [M1]
A←NOT(A)
命令
00 101 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
1 | 1 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_low PA_NOT PR_Write_A PR_InvertIn PF_Write_H PF_Select_H_bit17 PF_Write_N PF_Select_N_bit17 | |
cl↓ | |||
(E) | Pa_Ophd |
*NEG (X2/M2/T8) [M1\M1]
A←-A
命令
11 101 101
01 000 100
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
ボロー | -A = 0 | V | -A < 0 | 1 | ハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR PA_Select_0x0_high PA_Select_A_low PA_SUB PR_Write_A PR_InvertIn PF_Write_C PF_Select_C_bit26 PF_Write_Z PF_Select_Z_bit24 PF_Write_P/V PF_Select_P/V_bit25 PF_Write_S PF_Select_S_bit7 PF_Write_N PF_Select_N_bit17 PF_Write_H PF_Select_H_bit22 | |
cl↓ | |||
(E) | Pa_Ophd |
*CCF (X1/M1/T4) [M1]
Frag_C←NOT(Frag_C)
命令
00 111 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
Not(Frag_C) | 0 | Frag_C |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_F_low PA_NOT PF_Write_H PF_Select_H_bit30 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit0 | |
cl↓ | |||
(E) | Pa_Ophd |
*SCF (X1/M1/T4) [M1]
Frag_C←1
命令
00 110 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
1 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PF_Write_H PF_Select_H_bit16 PF_Write_N PF_Select_N_bit16 PF_Write_C PF_Select_C_bit17 | |
cl↓ | |||
(E) | Pa_Ophd |
NOP (X1/M1/T4) [M1]
何もしない
命令
00 000 000
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
HALT (X1/M1/T4) [M1]
CPUを停止させる
命令
01 110 110
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | P2_Set_LHALT | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
DI (X1/M1/T4) [M1]
IFF1/IFF2←0
命令
11 110 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_IFF1 P2_Reset_IFF2 | |
cl↓ | |||
(E) | Pa_Ophd |
EI (X1/M1/T4) [M1]
IFF1/IFF2←1
命令
11 111 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_IFF1 P2_Set_IFF2 | |
cl↓ | |||
(E) | Pa_Ophd |
IM 0 (X2/M2/T8) [M1\M1]
割り込みモードを0に
命令
11 101 101
01 000 110
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR P2_IM0 | |
cl↓ | |||
(E) | Pa_Ophd |
IM 1 (X2/M2/T8) [M1\M1]
割り込みモードを1に
命令
11 101 101
01 010 110
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR P2_IM1 | |
cl↓ | |||
(E) | Pa_Ophd |
IM 2 (X2/M2/T8) [M1\M1]
割り込みモードを2に
命令
11 101 101
01 011 110
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR P2_IM2 | |
cl↓ | |||
(E) | Pa_Ophd |
16bit算術演算
*ADD HL,ss (X1/M3/T11) [M1+7]
HL←HL+ss
命令
00 ss1 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
16bitキャリー | 0 | 16bitハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 7 | cl↑ | PA_Select_HL_high PA_Select_BC/DE/HL/SP_low PA_ADD PR_Write_H PR_Write_L PF_Write_C PF_Select_C_bit32 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit31 |
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | cl↑ | ||
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
*ADC HL,ss (X2/M4/T15) [M1\M1+7]
HL←HL+ss+Frag_C
命令
11 101 101
01 ss1 010
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
16bitキャリー | HL+ss+Frag_C = 0 | V | HL+ss+Frag_C < 0 | 0 | 16bitハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 7 | cl↑ | PA_Select_HL_high PA_Select_BC/DE/HL/SP_low PA_ADC PR_Write_H PR_Write_L PF_Write_C PF_Select_C_bit32 PF_Write_Z PF_Select_Z_bit34 PF_Write_P/V PF_Select_P/V_bit33 PF_Write_S PF_Select_S_bit15 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit31 |
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | cl↑ | ||
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*SBC HL,ss (X2/M4/T15) [M1\M1+7]
HL←HL-ss-Frag_C
命令
11 101 101
01 ss0 010
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
16bitボロー | HL-ss-Frag_C = 0 | V | HL-ss-Frag_C < 0 | 1 | 16bitハーフボロー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XOTR | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 7 | cl↑ | PA_Select_HL_high PA_Select_BC/DE/HL/SP_low PA_SBC PR_Write_H PR_Write_L PF_Write_C PF_Select_C_bit36 PF_Write_Z PF_Select_Z_bit34 PF_Write_P/V PF_Select_P/V_bit33 PF_Write_S PF_Select_S_bit15 PF_Write_N PF_Select_N_bit17 PF_Write_H PF_Select_H_bit35 |
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | cl↑ | ||
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XOTR | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD IX,pp (X2/M4/T15) [M1\M1+7]
IX←IX+pp
命令
11 011 101
00 pp1 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
16bitキャリー | 0 | 16bitハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 7 | cl↑ | PA_Select_IX_high PA_Select_BC/DE/IX/SP_low PA_ADD PR_Write_IX_high PR_Write_IX_low PF_Write_C PF_Select_C_bit32 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit31 |
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | cl↑ | ||
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX | |
cl↓ | |||
(E) | Pa_Ophd |
*ADD IY,rr (X2/M4/T15) [M1\M1+7]
IY←IY+rr
命令
11 111 101
00 rr1 001
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
16bitキャリー | 0 | 16bitハーフキャリー |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 7 | cl↑ | PA_Select_IY_high PA_Select_BC/DE/IY/SP_low PA_ADC PR_Write_IY_high PR_Write_IY_low PF_Write_C PF_Select_C_bit32 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit31 |
cl↓ | |||
5 | cl↑ | ||
cl↓ | |||
6 | cl↑ | ||
cl↓ | |||
7 | cl↑ | ||
cl↓ | |||
8 | cl↑ | ||
cl↓ | |||
9 | cl↑ | ||
cl↓ | |||
10 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY | |
cl↓ | |||
(E) | Pa_Ophd |
INC ss (X1/M1/T6) [M1+2]
ss←ss+1
命令
00 ss0 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_BC/DE/HL/SP_high PA_Select_0x1_low PA_ADD PR_Write_B/D/H/SP_high PR_Write_C/E/L/SP_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
INC IX (X2/M2/T10) [M1\M1+2]
IX←IX+1
命令
11 011 101
00 100 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_IX_high PA_Select_0x1_low PA_ADD PR_Write_IX_high PR_Write_IX_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX | |
cl↓ | |||
(E) | Pa_Ophd |
INC IY (X2/M2/T10) [M1\M1+2]
IY←IY+1
命令
11 111 101
00 100 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_IY_high PA_Select_0x1_low PA_ADD PR_Write_IY_high PR_Write_IY_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY | |
cl↓ | |||
(E) | Pa_Ophd |
DEC ss (X1/M1/T6) [M1+2]
ss←ss-1
命令
00 ss1 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_BC/DE/HL/SP_high PA_Select_0x1_low PA_SUB PR_Write_B/D/H/SP_high PR_Write_C/E/L/SP_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 | |
cl↓ | |||
(E) | Pa_Ophd |
DEC IX (X2/M2/T10) [M1\M1+2]
IX←IX-1
命令
11 011 101
00 101 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIX | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_IX_high PA_Select_0x1_low PA_SUB PR_Write_IX_high PR_Write_IX_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIX | |
cl↓ | |||
(E) | Pa_Ophd |
DEC IY (X2/M2/T10) [M1\M1+2]
IY←IY-1
命令
11 111 101
00 101 011
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XIY | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | ||
cl↓ | |||
4 | 2 | cl↑ | PA_Select_IY_high PA_Select_0x1_low PA_SUB PR_Write_IY_high PR_Write_IY_low |
cl↓ | |||
5 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Reset_XIY | |
cl↓ | |||
(E) | Pa_Ophd |
循環および桁移動
*RLCA (X1/M1/T4) [M1]
Frag_C←A_7
A←[A_6,…,A_0,A_7]
命令
00 000 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A_7 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_low PA_RLC PR_Write_A PR_InvertIn PF_Write_C PF_Select_C_bit38 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*RLA (X1/M1/T4) [M1]
Frag_C←A_7;A←[A_6,…,A_0,Frag_C]
命令
00 010 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A_7 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_low PA_RL PR_Write_A PR_InvertIn PF_Write_C PF_Select_C_bit38 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*RRCA (X1/M1/T4) [M1]
Frag_C←A_0
A←[A_0,A_7,…,A_1]
命令
00 001 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A_0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_low PA_RRC PR_Write_A PR_InvertIn PF_Write_C PF_Select_C_bit37 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*RRA (X1/M1/T4) [M1]
Frag_C←A_0; A←[Frag_C,A_7,…,A_1]
命令
00 011 111
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
A_0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 PA_Select_A_low PA_RR PR_Write_A PR_InvertIn PF_Write_C PF_Select_C_bit37 PF_Write_N PF_Select_N_bit16 PF_Write_H PF_Select_H_bit16 | |
cl↓ | |||
(E) | Pa_Ophd |
*RLC r (X2/M2/T8) [M1\M1]
Frag_C←r_7
r←[r_6,…,r_0,r_7]
命令
11 001 011
00 000 rrr
フラグ変化
C | Z | P/V | S | N | H |
---|---|---|---|---|---|
r_7 | [r_6,…,r_0,r_7] = 0 | P | [r_6,…,r_0,r_7] < 0 | 0 | 0 |
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |
cl↓ | |||
3 | cl↑ | PR_Reset_XPT P2_Set_CM1 P2_Set_XBIT | |
cl↓ | |||
0 | M1 | cl↑ | |
cl↓ | |||
1(W) | cl↑ | ||
cl↓ | |||
2 | cl↑ | PR_Inc_PC | |